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ASAHI KASEI
[AK4586]
AK4586
Multi-channel Audio CODEC with DIR
GENERAL DESCRIPTION The AK4586 is a single chip CODEC that includes two channels of ADC and six channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. The AK4586 also has a digital audio receiver (DIR) compatible with 96kHz, 24bits. The AK4586 can automatically detect a Non-PCM bit stream. The digital audio output can be selected from the ADC output or the digital input. Control may be set directly by programmed through a separate serial interface. The AK4586 has a dynamic range of 100dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. The AK4586 also has the balance volume control corresponding to the AC-3 system. The AK4586 is available in a small 44pin LQFP package which will reduce system space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES 2ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Single-Ended Input - S/(N+D): 90dB - Dynamic Range, S/N: 100dB - Digital HPF for offset cancellation - Overflow flag 6ch 24bit DAC - 128x Oversampling - Sampling Rate up to 96kHz - 24bit 8 times Digital Filter - Single-Ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - Individual channel digital volume with 256 levels and 0.5dB step - Soft mute - Zero Detect Function 4 inputs 24bit DIR - Supports IEC60958 consumer mode, S/PDIF, EIAJ CP1201 consumer mode - Low jitter Analog PLL - PLL Lock Range: 32k 96kHz - Clock Source: PLL or X'tal - 4 channel Receivers input and 1 through transmission output - De-emphasis for 32kHz, 44.1kHz and 48kHz - Dedicated Detect Pins Non-PCM Bit Stream Detect, DTS-CD Bit Stream Detect, Validity Flag Detect, 96kHz Sampling Detect, Unlock & Parity Error Detect, Emphasis Detect, fs change Detect - Supports up to 24bit Audio Data Format - Audio I/F: Master or Slave Mode - 32bits Channel Status Buffer
MS0097-E-01 -12001/12
ASAHI KASEI
[AK4586]
- Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream - Master Clock Outputs:128fs/256fs/512fs I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM High Jitter Tolerance TTL Level Digital I/F 4-wire Serial and I2C Bus P I/F for mode setting Extenal Master Clock Input: - 256fs, 384fs or 512fs for fs=44.1kHz to 48kHz - 128fs, 192fs or 256fs for fs=88.2kHz to 96kHz Power Supply: 4.5 to 5.5V Power Supply for output buffer: 2.7 to 5.5V Small 44pin LQFP Block Diagram
CSN CCLK CDTI CDTO
LIN
ADC
HPF
Audio I/F
MCLK
XTI
P I/F
X'tal Oscillator
XTO
RIN
ADC
HPF
Clock Recovery
LOUT1
Clock Generator
MCKO TX
LPF
DAC
DATT DAIF Decoder DEM Input Selector
ROUT1
LPF
DAC
DATT
LOUT2
LPF
DAC
DATT
RX1 RX2 RX3 RX4
ROUT2
LPF
DAC
DATT
SDOUT BICK LRCK SDIN1 SDIN2 SDIN3
SDTO BICK LRCK SDTI1 SDTI2 SDTI3
LOUT3
LPF
DAC
DATT
ROUT3
LPF
DAC
DATT
MS0097-E-01 -2-
2001/12
ASAHI KASEI
[AK4586]
Ordering Guide
AK4586VQ AKD4586 -40 +85C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4586
Pin Layout
SLAVE
RX3
RX4
TST
PVSS
RX2
42
R 35
44
43
41
40
39
38
36
37
34
PVDD
PDN
RX1
I2C
XTO XTI/EXTCLK DVDD DVSS TVDD TX MCKO LRCK BICK SDTO SDTI1
1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 18 19 20 13 17 21 22 Top View
33 32 31 30
RIN LIN ROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3 DZF1 VCOM VREFH
AK4586VQ
29 28 27 26 25 24 23
CAD1/CDTO
CAD0/CSN
SCL/CCLK
DZF2/OVF
SDA/CDTI
SDTI2
SDTI3
MS0097-E-01 -3-
AVDD
AVSS
INT0
INT1
2001/12
ASAHI KASEI
[AK4586]
Compatibility with AK4527B/29
Functions ADC S/(N+D) ADC Dynamic Range, S/N DAC channel Master mode Parallel mode Read operation for internal register Chip address at 4-wire serial mode AK4527B/29 92dB 102dB 6ch/8ch Not available Available Not available 2bit selectable AK4586 90dB 100dB 6ch Available Not available Available fixed to "00"
Compatibility with AK4112A
Functions Power supply Rock range Master clock output External master clock input Detect pins DTS-CDdetect CRC Parallel mode I2C bus mode Digital input level AK4112A 2.7 3.6V 22k 108kHz 2 pins 256fs/512fs 4 pins Not available Available Available Not available CMOS AK4586 4.5 5.5V 32k 96kHz 1 pin 256fs/384fs/512fs for Normal speed 128fs/192fs/256fs for Double speed 2 pins Available Not available Not available Available TTL
MS0097-E-01 -4-
2001/12
ASAHI KASEI
[AK4586]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name XTO XTI EXTCLK DVDD DVSS TVDD TX MCKO LRCK BICK SDTO SDTI1 SDTI2 SDTI3 INT0 INT1 CDTO CAD1 CDTI SDA CCLK SCL CSN CAD0 DZF2 I/O O I I O O I/O I/O O I I I O O O I I I/O I I I I O Function X'tal Output Pin X'tal Input Pin External Master Clock Input Pin Digital Power Supply Pin, 4.5V5.5V Digital Ground Pin, 0V Output Buffer Power Supply Pin, 2.7V5.5V Transmit channel (through data) Output Pin Master Clock Output Pin Input/Output Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Output Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin Interrupt 0 pin Interrupt 1 pin Control Data Output Pin in 4-wire serial control mode Chip Address 1 Pin in I2C bus control mode Control Data Input Pin in 4-wire serial control mode Control Data Input/Output Pin in I2C bus control mode Control Data Clock Pin in 4-wire serial control mode Control Data Clock Pin in I2C bus control mode Chip Select Pin in 4-wire serial control mode Chip Address 0 Pin in I2C bus control mode Zero Input Detect 2 Pin (Note 1) When the input data of the group 1 follow total 8192 LRCK cycles with "0" input data, this pin goes to "H". Analog Input Overflow Detect Pin (Note 2) This pin goes to "H" if the analog input of Lch or Rch is overflows. Analog Ground Pin, 0V Analog Power Supply Pin, 4.5V5.5V
OVF 21 22 AVSS AVDD
O -
MS0097-E-01 -5-
2001/12
ASAHI KASEI
[AK4586]
No. 23 24 25
Pin Name VREFH VCOM DZF1
I/O I O O
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
LOUT3 ROUT3 LOUT2 ROUT2 LOUT1 ROUT1 LIN RIN PVDD R PVSS RX4 SLAVE RX3 TST RX2 I2C RX1 PDN
O O O O O O I I I I I I I I I I
Function Positive Voltage Reference Input Pin, AVDD Common Voltage Output Pin, AVDD/2 Large external capacitor around 2.2F is used to reduce power-supply noise. Zero Input Detect 1 Pin (Note 1) When the input data of the group 1 follow total 8192 LRCK cycles with "0" input data, this pin goes to "H". DAC3 Lch Analog Output Pin DAC3 Rch Analog Output Pin DAC2 Lch Analog Output Pin DAC2 Rch Analog Output Pin DAC1 Lch Analog Output Pin DAC1 Rch Analog Output Pin Lch Analog Input Pin Rch Analog Input Pin PLL Power Supply Pin, 4.5V5.5V External Resistor Pin 18k +/-1% resistor to PVSS externally. PLL Ground Pin, 0V Receiver Channel 4 Pin (Internal biased pin) Slave Mode Pin "L": Master mode or Slave mode, "H": Slave mode Receiver Channel 3 Pin (Internal biased pin) Test Pin This pin should be connected to DVSS. Receiver Channel 2 Pin (Internal biased pin) Control Mode Select Pin "L": 4-wire Serial, "H": I2C Bus Receiver Channel 1 Pin (Internal biased pin) Power-Down & Reset Pin When "L", the AK4586 is powered-down, all output pins go to "L" and the control registers are reset to default state. If the state of CAD1-0 changes, then the AK4586 must be reset by PDN.
Notes: 1. The group 1 and 2 can be selected by DZFM2-0 bits. 2. This pin becomes OVF pin if OVFE bit is set to "1". 3. All input pins except internal biased pins should not be left floating.
MS0097-E-01 -6-
2001/12
ASAHI KASEI
[AK4586]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, PVSS=0V; Note 4) Parameter Power Supplies Analog Digital PLL Output buffer |AVSS-DVSS| (Note 5) |AVSS-PVSS| (Note 5) Input Current (any pins except for supplies) Analog Input Voltage Digital Input Voltage (XTI/EXTCLK, SDTI1-3, CDTI/SDA, CCLK/SCL, CSN/CAD0 pins) (LRCK, BICK, CDTO/CAD1 pins) (RX1-4, SLAVE, TST, I2C, PDN pins) Ambient Temperature (power applied) Storage Temperature Symbol AVDD DVDD PVDD TVDD GND1 GND2 IIN VINA VIND1 VIND2 VIND3 Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 -65 max 6.0 6.0 6.0 6.0 0.3 0.3 10 AVDD+0.3 DVDD+0.3 TVDD+0.3 PVDD+0.3 85 150 Units V V V V V V mA V V V V C C
Notes: 4. All voltages with respect to ground. 5. AVSS, DVSS and PVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, PVSS=0V; Note 4) Parameter Power Supplies Analog (Note 6) Digital PLL Output buffer Symbol AVDD DVDD PVDD TVDD min 4.5 4.5 4.5 2.7 typ 5.0 5.0 5.0 5.0 max 5.5 5.5 5.5 5.5 Units V V V V
Notes: 4. All voltages with respect to ground. 6. The power up sequence between AVDD, DVDD, PVDD and TVDD is not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0097-E-01 -7-
2001/12
ASAHI KASEI
[AK4586]
ANALOG CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=48kHz 82 90 dB fs=96kHz 78 86 dB DR (-60dBFS) fs=48kHz, A-weighted 92 100 dB fs=96kHz, A-weighted 91 100 dB S/N (Note 7) fs=48kHz, A-weighted 92 100 dB fs=96kHz, A-weighted 91 100 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 ppm/C Input Voltage fs=48kHz AIN=0.62xVREFH 2.90 3.10 3.30 Vpp fs=96kHz AIN=0.65xVREFH 3.05 3.25 3.45 Vpp Input Resistance (Note 8) 15 25 k Power Supply Rejection (Note 9) 50 dB DAC Analog Output Characteristics Resolution 24 Bits S/(N+D) fs=48kHz 80 90 dB fs=96kHz 78 86 dB DR (-60dBFS) fs=48kHz, A-weighted 95 106 dB fs=96kHz, A-weighted 94 106 dB S/N (Note 10) fs=48kHz, A-weighted 95 106 dB fs=96kHz, A-weighted 94 106 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/C Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp Load Resistance 5 k Power Supply Rejection (Note 9) 50 dB Power Supplies Power Supply Current Normal Operation (PDN = "H") (Note 11) mA 54 39 AVDD mA 14 9 PVDD mA 42 28 DVDD+TVDD fs=48kHz (Note 12) mA 59 39 fs=96kHz A 200 80 Power-down mode (PDN = "L") (Note 13) Notes: 7. S/N measured by CCIR-ARM is 96dB(@fs=48kHz). 8. Input resistance is 16k typically at fs=96kHz. 9. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 10. S/N measured by CCIR-ARM is 102dB(@fs=48kHz). 11. CL=20pF, X'tal=24.576MHz, CM1-0= "10", OCKS= "10". 12. TVDD=3mA(typ). 13. In the power-down mode. RX inputs are open and all digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS.
MS0097-E-01 -8-
2001/12
ASAHI KASEI
[AK4586]
FILTER CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PVDD=4.55.5V; TVDD=2.75.5V; fs=48kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband (Note 14) PB 0 0.1dB -0.2dB -3.0dB Stopband SB 29.4 Passband Ripple PR Stopband Attenuation SA 65 Group Delay (Note 15) GD Group Delay Distortion GD ADC Digital Filter (HPF): Frequency Response (Note 14) -3dB FR -0.1dB DAC Digital Filter: Passband (Note 14) -0.1dB PB 0 -6.0dB Stopband SB 26.2 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 15) GD DAC Digital Filter + Analog Filter: FR Frequency Response: 0 20.0kHz FR 40.0kHz (Note 16) typ max 18.9 0.1 17.0 0 1.0 6.5 21.8 0.02 19.1 0.2 0.3 Units kHz kHz kHz kHz dB dB 1/fs s Hz Hz kHz kHz kHz dB dB 1/fs dB dB
20.0 23.0
24.0
Notes: 14. The passband and stopband frequencies scale with fs. For example, 21.8kHz at -0.1dB is 0.454 x fs. The reference frequency of these responses is 1kHz. 15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 16. fs=96kHz.
DC CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PVDD=4.55.5V; TVDD=2.75.5V) Parameter Symbol VIH High-Level Input Voltage (Except XTI pin) VIH (XTI pin) VIL Low-Level Input Voltage (Except XTI pin) VIL (XTI pin) VAC Input Voltage at AC Coupling (Note 17) High-Level Output Voltage VOH (Except TX, DZF1, DZF2/OVF pins: Iout=-400A) VOH (TX pin: Iout=-400A) VOH (DZF1, DZF2/OVF pins: Iout=-400A) Low-Level Output Voltage VOL (Except SDA pin: Iout= 400A) VOL (SDA pin: Iout= 3mA) Iin Input Leakage Current Notes: 17. In case of connecting capacitance to XTI pin (refer to Figure 4). min 2.2 70%DVDD 40%DVDD TVDD-0.5 DVDD-0.5 AVDD-0.5 typ max 0.8 30%DVDD 0.5 0.4 10 Units V V V V Vpp V V V V V A
MS0097-E-01 -9-
2001/12
ASAHI KASEI
[AK4586]
SWITCHING CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PVDD=4.55.5V; TVDD=2.75.5V; CL=20pF) Parameter Symbol min Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 External Clock 11.2896 fCLK 256fsn, 128fsd: 27 tCLKL Pulse Width Low 27 tCLKH Pulse Width High 16.9344 fCLK 384fsn, 192fsd: 20 tCLKL Pulse Width Low 20 tCLKH Pulse Width High 22.5792 fCLK 512fsn, 256fsd: 15 tCLKL Pulse Width Low 15 tCLKH Pulse Width High MCKO output Frequency fMCK 5.6448 Duty (Note 18) dMCK 40 PLL Clock Recover Frequency fPLL 32 LRCK Timing TDM= "0" LRCK frequency Normal Speed Mode fsn 32 Double Speed Mode fsd 88.2 Duty Cycle Duty 45 TDM= "1" (Slave mode) LRCK frequency fsn 32 "H" time tLRH 1/256fs "L" time tLRL 1/256fs TDM= "1" (Master mode) 32 fsn LRCK frequency tLRH "H" time (Note 19) typ max Units
24.576 12.288
MHz MHz ns ns MHz ns ns MHz ns ns MHz % kHz
18.432
24.576
50
24.576 60 96
48 96 55 48
kHz kHz % kHz ns ns kHz ns
48 1/8fs
Notes: 18. Except the case CLKDIV= "0" for the external clock input. CL=15pF when MCKO is above 22.5792MHz. 19. "L" time at I2S format.
MS0097-E-01 - 10 -
2001/12
ASAHI KASEI
[AK4586]
Parameter Audio Interface Timing (Slave mode) TDM= "0" BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 20) BICK "" to LRCK Edge (Note 20) LRCK to SDTO(MSB) (Note 21) BICK "" to SDTO SDTI1-3, DAUX Hold Time SDTI1-3, DAUX Setup Time TDM= "1" BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 20) BICK "" to LRCK Edge (Note 20) BICK "" to SDTO SDTI1 Hold Time SDTI1 Setup Time Audio Interface Timing (Master mode) TDM= "0" BICK Frequency BICK Duty BICK "" to LRCK Edge BICK "" to SDTO SDTI1-3 Hold Time SDTI1-3 Setup Time TDM= "1" BICK Frequency BICK Duty BICK "" to LRCK Edge BICK "" to SDTO SDTI1 Hold Time SDTI1 Setup Time
Symbol
min
typ
max
Units
tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS
160 65 65 45 45 40 40 40 25 81 32 32 20 20 20 10 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS
64fs 50 -20 40 25 256fs 50 -12 10 10 12 20 20 40
Hz % ns ns ns ns Hz % ns ns ns ns
Notes: 20. BICK rising edge must not occur at the same time as LRCK edge. 21. MSB justified format.
MS0097-E-01 - 11 -
2001/12
ASAHI KASEI
[AK4586]
Parameter Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" CDTO Delay CSN "" to CDTO Hi-Z Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 22) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 23) PDN "" to SDTO valid (Note 24)
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP tPD tPDV
min 200 80 80 40 40 150 50 50
typ
max
Units ns ns ns ns ns ns ns ns ns ns kHz s s s s s s s s s s ns ns 1/fs
45 70 4.7 4.0 4.7 4.0 4.7 0 0.25 4.0 0 150 522 100 1.0 0.3 50
Notes: 22. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 23. The AK4586 can be reset by bringing PDN "L" to "H" upon power-up. 24. These cycles are the number of LRCK rising from PDN rising. 25. I2C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I C components conveys a license under the Philips 2 2 2 I C patent to use the components in the I C system, provided the system conform to the I C specifications defined by Philips.
2
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25C; AVDD, DVDD, PVDD=4.5~5.5V; TVDD=2.7~5.5V) Parameter Symbol Input Resistance Zin Input Voltage VTH Input Hysteresis VHY Input Sample Frequency fs min 200 32 typ 10 50 max Units k mVpp mV kHz
96
MS0097-E-01 - 12 -
2001/12
ASAHI KASEI
[AK4586]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fMCKO
MCKO tMCKH tMCKL
50%TVDD dMCK = tMCKH x fMCK x 100 = tMCKL x fMCK x 100
1/fs VIH VIL tLRH tLRL Duty = tLRH x fs x 100 = tLRL x fs x 100
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing (TDM= "0")
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs VIH VIL tLRH tLRL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing (TDM= "1")
MS0097-E-01 - 13 -
2001/12
ASAHI KASEI
[AK4586]
LRCK tBLR tLRB
VIH VIL
BICK
VIH VIL tLRS tBSD
SDTO tSDS
50%TVDD
tSDH VIH VIL
SDTI
Audio Interface Timing (Slave mode, TDM= "0")
VIH VIL tBLR tLRB VIH VIL tBSD
LRCK
BICK
SDTO tSDS
50%TVDD
tSDH VIH VIL
SDTI
Audio Interface Timing (Slave mode, TDM= "1")
LRCK
50%TVDD
tMBLR BICK 50%TVDD
tBSD 50%TVDD
SDTO tSDS tSDH
SDTI
VIH VIL
Audio Interface Timing (Master Mode)
MS0097-E-01 - 14 -
2001/12
ASAHI KASEI
[AK4586]
VIH CSN tCSS tCCKL tCCKH CCLK tCDH VIH VIL tCDS VIL
CDTI
C1
C0
R/W
A4
VIH VIL
CDTO
Hi-Z
WRITE/READ Command Input Timing (4-wire serial mode)
tCSW VIH CSN tCSH VIH VIL VIL
CCLK
CDTI
D3
D2
D1
D0
VIH VIL
CDTO
Hi-Z
WRITE Data Input Timing (4-wire serial mode)
VIH CSN VIL
CCLK
VIH VIL
CDTI
A1
A0
VIH VIL tDCD
CDTO
Hi-Z
D7
D6
D5
50%TVDD
READ Data Output Timing 1 (4-wire serial mode)
MS0097-E-01 - 15 -
2001/12
ASAHI KASEI
[AK4586]
tCSW CSN VIH VIL tCSH CCLK VIH VIL
CDTI
VIH VIL tCCZ
CDTO
D3
D2
D1
D0
50%TVDD
READ Data Output Timing 2 (4-wire serial mode)
VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
I2C Bus mode Timing
tPD
PDN
VIH VIL tPDV
SDTO
50%TVDD
Power-down & Reset Timing
MS0097-E-01 - 16 -
2001/12
ASAHI KASEI
[AK4586]
OPERATION OVERVIEW Non-PCM (AC-3, MPEG, etc.), DTS-CD Bitstream Detect
The AK4586 has the Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby "AC-3 Data Stream in IEC60958 Interface" is detected, the AUTO bit goes to "1". The 16bit mode Non-PCM preamble is not detected. The AUTO bit remains "0" at that time. The 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO bit "1". Once the AUTO is set to "1", it will remain "1" until 4096 frames pass through the chip without additional sync pattern being detected. When those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers 0DH-10H. The AK4586 also has the DTS-CD stream auto detect function. When the AK4586 detects the DTS-CD bitstreams, the DTSCD bit goes to "1". When the next sync code does not come within 4096 flames, the DTSCD bit goes to "0" until the AK4586 detects the stream again.
Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 32kHz to 96kHz and the lock time is less than 20ms. The 96kHz detect bit RFS96 goes to "1" when the sampling rate is 88.2kHz or more and "0" at 48kHz or less. PLL loses lock when the received sync interval is incorrect.
Clock Operation Mode
The CM0 and CM1 bits select the clock source of MCKO and the data source of SDTO (Table 1). In mode 2, the clock source is switched from PLL to X'tal when PLL goes to the unlock state. In mode 3, the clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored. Mode 0 1 2 3 CM1 0 0 1 1 CM0 0 1 0 UNLOCK PLL X'tal Clock source ON OFF PLL OFF ON X'tal 0 ON ON PLL 1 ON ON X'tal 1 ON ON X'tal ON: Oscillation (Power-up), OFF: STOP (Power-down) Table 1. Clock Operation Mode Select SDTO RX ADC RX ADC ADC
Default
System Clock
The AK4586 has the master clock output pin, MCKO. This clock is derived from either the recovered clock or from the crystal oscillator. In the PLL mode, the frequency of the master clock output (MCKO) is set by OCKS0 and OCKS1 bits as shown in Table 2. 96kHz sampling is not supported at mode 2. MCKO goes to "L" when the AK4586 detect 96kHz sampling at mode 2. Sampling speed mode is set by RFS96 or XFS96 bit (Table 3). In the x'tal mode, the x'tal frequency rate to fs is set by ICKS1-0 bits (Table 4). In the x'tal mode, the frequency of the MCKO pin becomes half of the crystal oscillator if the CLKDIV bit is set to "1" (Table 5). ICKS1-0 and XFS96 bits should be changed while RSTN bit is "0". If the external clocks are not present, the AK4586 should be in the power-down mode (PDN= "L") or in the reset mode (RSTN= "0"). Mode 0 1 2 3 OCKS1 0 0 1 1 OCKS0 0 1 0 1 MCKO 256fs 128fs 512fs fs 32kHz~96kHz 32kHz~96kHz 32kHz~48kHz Reserved
Default
Table 2. Master Clock Output Frequency Select (PLL mode)
MS0097-E-01 - 17 -
2001/12
ASAHI KASEI
[AK4586]
Clock mode X'tal mode
AFS96 x 0
RFS96 x x 0 1
PLL mode 1
XFS96 0 1 0 1 x x
Sampling Speed (fs) Normal Speed Mode 44.1kHz~48kHz Double Speed Mode 88.2kHz~96kHz Normal Speed Mode 32kHz~48kHz Double Speed Mode 88.2kHz~96kHz Normal Speed Mode 32kHz~48kHz Double Speed Mode 88.2kHz~96kHz
Table 3. Sampling Speed Mode (x: Don't care)
Mode 0 1 2 3
ICKS1 0 0 1 1
ICKS0 0 1 0 1
Normal 256fs 384fs 512fs 256fs
Double 128fs 192fs 256fs 256fs
Default
Table 4. Master Clock Input Frequency Select (X'tal mode) (In the x'tal mode, ADC is automatically powered down at 128fs and 192fs in the double speed mode.)
CLKDIV 0 1
MCKO XTI x1 XTI x1/2
Default
Table 5. Master Clock Output Select (X'tal mode)
XTI x1/2
CLKDIV MCKO 256fs 128fs PLL 512fs CM1-0
OCKS1-0
Figure 1. Master Clock Output Select
MS0097-E-01 - 18 -
2001/12
ASAHI KASEI
[AK4586]
Clock Source
The following circuits are available to feed the clock to XTI pin of AK4586. 1) X'tal
XTI
XTO
AK4586
Figure 2. X'tal mode Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock
XTI External Clock(5V)
XTO
AK4586
Figure 3. External clock mode(5V) Note: Input clock must not exceed DVDD.
XTI External Clock(3.3V)
XTO
AK4586
Figure 4. External clock mode(3.3V) Note: 3.3V external clock should be AC coupled. The amplitude of the clock should be larger than 40%DVDD. 3) Fixed to the Clock Operation Mode 0
XTI
XTO
AK4586
Figure 5. Off mode
MS0097-E-01 - 19 -
2001/12
ASAHI KASEI
[AK4586]
Sampling Frequency and Pre-emphasis Detect
The AK4586 outputs the encoded information of sampling frequency and pre-emphasis in channel status to FS0, FS1 and PEM bits in control register. These information are output from channel 1 at default. It can be switched to channel 2 by CS12 bit in control register. FS1 0 0 1 1 FS0 0 1 0 1 fs 44.1kHz Reserved 48kHz 32kHz Byte 3 Bits 0-3 0000 all others 0100 1100
Table 6. Sampling frequency information in Consumer Mode PEM 0 1 Pre-emphasis OFF ON Byte 0 Bits 3-5 0X100 0X100
Table 7. Pre-emphasis information in Consumer Mode
MS0097-E-01 - 20 -
2001/12
ASAHI KASEI
[AK4586]
De-emphasis Filter Control
The AK4586 includes the digital de-emphasis filter (tc=50/15s) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). When DEAU bit = "1", the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. The AK4586 goes to this mode at default and the de-emphasis filter is controlled by the status bits in channel 1 (Table 8). DEM1-0 and DFS bits can control the de-emphasis filter when DEAU is "0" (Table 9). The internal de-empahsis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis mode is OFF. The internal de-emphasis filter is bypassed if the Non-PCM or the DTS-CD bitstream is detected at DEAU= "1". The internal de-emphasis filter is bypassed if bit 0 of the channel status byte 0 is "1". RFS96 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 DEM 44.1kHz OFF 48kHz 32kHz OFF OFF OFF OFF
Default
Table 8. De-emphasis Auto Control at DEAU="1" and PEM="1"
Sampling Speed Normal Speed Normal Speed Normal Speed Normal Speed Double Speed Double Speed Double Speed Double Speed
DEM1 0 0 1 1 0 0 1 1
DEM0 0 1 0 1 0 1 0 1
DEM 44.1kHz OFF 48kHz 32kHz OFF OFF OFF OFF
Default
Table 9. De-emphasis Manual Control at DEAU="0" and PEM="1"
System Reset and Power-Down
The AK4586 has a power-down mode for all circuits by PDN pin or can be partially powered-down by internal register. The AK4586 should be reset once by bringing PDN pin = "L" upon power-up. ADC, DAC and PLL are powered-down at PWVRN= "0". PDN L x x x x x x PWADN x 0 x x x x x PWDAN x x 0 x x x x PWVRN x x x 0 x x x RSTN x x x x 0 x x CM1-0 x x x x x 00 01 Function All power down ADC power down DAC power down VREF power down Timing Reset X'tal power down PLL power down Register initialization Yes No No No No No No
Table 10. Reset & Power Down
MS0097-E-01 - 21 -
2001/12
ASAHI KASEI
[AK4586]
Biphase Input and Through Output
Four receiver inputs (RX1-4) are available. Each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mV or more. IPS1-0 selects the receiver channel (Table 11), and OPS1-0 selects the source of the bit stream driving the transmit channel (TX, Table 12). The TX output can be stopped by setting TXE bit "0". IPS1 0 0 1 1 IPS0 0 1 0 1 INPUT Data RX1 RX2 RX3 RX4
Default
Table 11. Recovery data select
OPS1 0 0 1 1
OPS0 0 1 0 1
INPUT Data RX1 RX2 RX3 RX4
Default
Table 12. Output data select
MS0097-E-01 - 22 -
2001/12
ASAHI KASEI
[AK4586]
Biphase signal input/output circuit
0.1uF 75 Coax RX 75
AK4586
Figure 6. Consumer Input Circuit (Coaxial Input) Note 1: In case of coaxial input, if a coupling level to this input from the next RX input line pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is possible to lower the coupling level by adding this decoupling capacitor. Note 2: Ground of RCA connector and terminator should be connected to PVSS of the AK4586 with low impedance on PC board. Optical Receiver Optical Fiber O/E
470 RX
AK4586
Figure 7. Consumer Input Circuit (Optical Input) In case of coaxial input, as the input level of RX line is small, be careful not to crosstalk among RX input lines. For example, by inserting the shield pattern among them. The AK4586 includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure 8 is a transformer of 1:1. 330 TX 100 DVSS 75 cable
T1 Figure 8. TX External Resistor Network
MS0097-E-01 - 23 -
2001/12
ASAHI KASEI
[AK4586]
Error Handling
There are the following eight factors which INT1-0 pins go to "H". 1. UNLOCK: "1" when the PLL goes UNLOCK state. The AK4586 loses lock when the distance between two preambles is not correct or when those preambles are not correct. 2. PAR: "1" when parity error or biphase coding error is detected. Updated every sub-frame cycle. Reading this register resets itself. 3. AUTO: "1" when Non-PCM Bit Stream is detected. 4. DTSCD: "1" when DTS-CD Bit Stream is detected. 5. AUDION: "1" when the "AUDIO" bit in recovered channel status indicates "1". 6. STC: "1" when FS1, FS0 or PEM bit changes. Reading this register resets itself. 7. V: "1" when validity flag is detected. 8. RFS96: "1" when fs=88.2kHz or more (RFS96 bit is set by XFS96 bit at x'tal mode or AFS96= "0"). INT1-0 pins output the ORed signal among those eight factors. However, each factor can be masked by each mask bit. When each bit masks those factors, the factor does not affect INT1-0 pins operation (those masks do not affect those resisters (UNLOCK, PAR, etc.) themselves). Once INT0 pin goes to "H", it maintains "H" for 1024 cycles (this value can be changed by EFH1-0 bits) after the all factors are removed. Once the PAR bit goes to "1", it holds "1" until reading the register. While the AK4586 loses lock, the channel status bits are not updated and hold the previous data. At initial state, INT0 outputs the ORed signal between UNLOCK and PAR. INT1 outputs the ORed signal among AUTO, DTSCD, AUDION and V. INT1-0 pins are "L" when the PLL is OFF (Clock Operation Mode 1). Register DTSCD AUDION x x x x x x 1 x x 1 x x x x x x Pin SDTO "L" Previous Data Output Output Output Output Output Output
UNLOCK 1 0 0 0 0 0 0 0
PAR x 1 0 0 0 0 0 0
AUTO x x 1 x x x x x
STC x x x x x 1 x x
V x x x x x x 1 x
RFS96 x x x x x x x 1
TX Output Output Output Output Output Output Output Output
Table 13. Error handling
MS0097-E-01 - 24 -
2001/12
ASAHI KASEI
[AK4586]
Error (UNLOCK, PAR,..) INT0 pin
(Error)
Hold Time (max: 4096/fs)
INT1 pin Register (PAR,STC) Register (except PAR,STC) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) Previous Data
Hold Time = 0
Hold "1"
Reset
READ 0EH
Free Run (fs: around 20kHz)
Normal Operation Figure 9. INT0/1 pin timing
MS0097-E-01 - 25 -
2001/12
ASAHI KASEI
[AK4586]
PDN pin ="L" to "H" Initialize Read 0EH
INT0/1 pin ="H"
Yes
No
Release Muting
Mute DAC output
Read 0EH
(Each Error Handling) No
INT0/1 pin ="H"
Yes
Figure 10. Error Handling Sequence Example
MS0097-E-01 - 26 -
2001/12
ASAHI KASEI
[AK4586]
Audio Serial Interface Format
Eight serial data formats can be selected by the DIF2-0 bits as shown in Table 14 at the SLAVE pin "L". If the SLAVE pin is "H", the AK4586 is fixed in the slave mode and two serial data format can be selected by the DIF0 bit. In all formats the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI1-3 are latched on the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are the slave mode, and BICK is available up to 128fs at fs=48kHz. In the format equal or less than 20bit (mode 0-2), LSBs in sub-frame are truncated. In mode 3-7, the last 4LSBs are auxiliary data (see Figure 11). When the Parity Error or Biphase Error occurs in a sub-frame, the AK4586 continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, the AK4586 outputs "0" from SDTO. Mode 4, 5, 6 and 7 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs.
sub-frame of IEC60958
0 preamble 34 Aux. LSB MSB 78 11 12 27 28 29 30 31 VUCP
MSB
LSB
23
0
AK4586 Audio Data (SDTO, MSB First)
Figure 11. Bit configuration Mode 0 1 2 3 4 5 6 7 6 7 SLAVE DIF 1 0 0 1 1 0 0 1 1 x SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S SDTI1-3 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I H/L I L/H I BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs 64-128fs 64-128fs I/O O O O O O O I I I I
0
2 0 0 0 0 1 1 1 1 x
1
0 0 1 0 1 0 1 0 1 0 1
Default
Table 14. Audio Data Format (TDM= "0")
MS0097-E-01 - 27 -
2001/12
ASAHI KASEI
[AK4586]
The audio serial interface format becomes the TDM I/F format if TDM bit is set to "1". In the TDM mode, the serial data of all DAC (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins is ignored. BICK should be fixed to 256fs. In the slave mode, "H" time and "L" time of LRCK should be 1/256fs at least. In the master mode, "H" time ("L" time at I2S mode) of LRCK is 1/8fs typically. LOOP1-0 should be set to "00" at the TDM mode. TDM mode cannot be used in double speed mode. Mode 8 9 10 11 12 13 14 15 14 15 SLAVE DIF 1 0 0 1 1 0 0 1 1 x SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S SDTI1-3 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK I/O O O O O O O I I I I BICK 256fs 256fs 256fs 256fs 256fs 256fs 256fs 256fs 256fs 256fs I/O O O O O O O I I I I
0
2 0 0 0 0 1 1 1 1 x
1
0 0 1 0 1 0 1 0 1 0 1
Table 15. Audio Data Format (TDM= "1")
LRCK(0)
0 1 2 15 16 17 31 0 1 2 15 16 17 31 0 1
BICK (0:64fs) SDTO(0)
15:MSB, 0:LSB 15 14 1 0 15 14 1 0
SDTI(I)
15:MSB, 0:LSB
15
14
1
0
15
14
1
0
Lch Data
Rch Data
Figure 12. Mode 0 Timing
LRCK(0)
0 1 2 9 10 11 12 31 0 1 2 9 10 11 12 31 0 1
BICK (0:64fs) SDTO(0)
23 23:MSB, 0:LSB 22 21 20 1 0 23 22 21 20 1 0
SDTI(I)
23 23:MSB, 0:LSB
22
21
20
1
0
23
22
21
20
1
0
Lch Data
Rch Data
Figure 13. Mode 3 Timing
MS0097-E-01 - 28 -
2001/12
ASAHI KASEI
[AK4586]
LRCK
0 1 2 21 22 23 24 31 0 1 2 21 22 23 24 31 0 1
BICK (64fs) SDTO(0)
23 22 21 2 1 0 23 22 3 2 1 0 23 22
23:MSB, 0:LSB
SDTI(I)
23
22 21
2
1
0
23 22
3
2
1
0
23 22
23:MSB, 0:LSB Lch Data Rch Data
Figure 14. Mode 4, 6 Timing Mode 4: LRCK, BICK: Output Mode 6: LRCK, BICK: Input
LRCK
0 1 2 22 23 24 25 31 0 1 2 21 22 23 24 25 31 0 1
BICK (64fs) SDTO(0)
23 22 21 2 1 0 23 22 3 2 1 0 23
23:MSB, 0:LSB
SDTI(I)
23
22 21
2
1
0
23 22
3
2
1
0
23
23:MSB, 0:LSB Lch Data Rch Data
Figure 15. Mode 5, 7 Timing Mode 5: LRCK, BICK: Output Mode 7: LRCK, BICK: Input
MS0097-E-01 - 29 -
2001/12
ASAHI KASEI
[AK4586]
256 BICK
LRCK BICK(256fs) SDTO(o)
15 14 0 15 14 0 15
Lch
32 BICK
Rch
32 BICK
0 15 14 0 15 14 0 15 14 0 15 14 0 15 14 0 15
SDTI1(i)
15 14
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK 64 BICK
Figure 16. Mode 8 Timing
256 BICK
LRCK BICK(256fs) SDTO(o)
23 22 0 23 22 0 23
Lch
32 BICK
Rch
32 BICK
0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23
SDTI1(i)
23 22
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK 64 BICK
Figure 17. Mode 11 Timing
MS0097-E-01 - 30 -
2001/12
ASAHI KASEI
[AK4586]
256 BICK
LRCK(mode 12) LRCK(mode 14) BICK(256fs) SDTO(o)
23 22 0 23 22 0 23 22
Lch
32 BICK
Rch
32 BICK
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22
SDTI1(i)
23 22
0
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK 64 BICK
Figure 18. Mode 12, 14 Timing Mode 12: LRCK, BICK: Output Mode 14: LRCK, BICK: Input
256 BICK
LRCK(mode 13) LRCK(mode 15) BICK(256fs) SDTO(o)
23 0 23 0 23
Lch
32 BICK
Rch
32 BICK
23 0 23 0 23 0 23 0 23 0 23
SDTI1(i)
23
0
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK 64 BICK
Figure 19. Mode 13, 15 Timing Mode 13: LRCK, BICK: Output Mode 15: LRCK, BICK: Input
MS0097-E-01 - 31 -
2001/12
ASAHI KASEI
[AK4586]
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and also scales with sampling rate (fs).
Overflow Detection
The AK4586 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to "1". OVF pin goes to "H" if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 17.0/fs = 354s@fs=48kHz). OVF is "L" for 522/fs (=10.9ms @fs=48kHz) after PDN = "", and then overflow detection is enabled.
Zero detection
The AK4586 has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM2-0 bits (Table 16). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2 channels. However DZF2 pin becomes OVF pin if OVFE bit is set to "1". For example, DZF1 is AND of all six channels and DZF2 is disabled ("L") at mode 0. When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK cycles, DZF1(DZF2) pin goes to "H". DZF1(DZF2) pin immediately goes to "L" if input data of any channels in the group 1(group 2) is not zero after going DZF1(DZF2) "H". Mode 0 1 2 3 4 5 6 7 DZFM 10 00 01 10 11 00 01 10 11 AOUT R1 L2 R2 L3 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1 DZF2 DZF2 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 disable (DZF1=DZF2 = "L")
2 0 0 0 0 1 1 1 1
L1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2
R3 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 Default
Table 16. Zero detect control
MS0097-E-01 - 32 -
2001/12
ASAHI KASEI
[AK4586]
Digital Attenuator
The AK4586 has channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 17). ATT7-0 00H 01H 02H : FDH FEH FFH Attenuation Level 0dB -0.5dB -1.0dB : -126.5dB -127.0dB MUTE (-)
Default
Table 17. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 18). Mode 0 1 2 3 ATS1 0 0 1 1 ATS0 0 1 0 1 ATT speed 7424/fs 1061/fs 256/fs Reserved
Default
Table 18. Transition time between set values of ATT7-0 bits The transition between set values is soft transition of 7425 levels in mode 0. It takes 7424/fs (155ms@fs=48kHz) from 00H(0dB) to FFH(MUTE) in mode 0. If PDN pin goes to "L", the ATTs are initialized to 00H. The ATTs are 00H when RSTN = "0". When RSTN return to "1", the ATTs fade to their current value. Digital attenuator is independent of soft mute function.
MS0097-E-01 - 33 -
2001/12
ASAHI KASEI
[AK4586]
Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to "1", the output signal is attenuated by - during 1024 LRCK cycles. When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE 1024/fs 0dB Attenuation (1) (3) 1024/fs
-
GD (2) AOUT (4) 8192/fs GD
DZF1,2
Notes: (1) The output signal is attenuated by - during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input have the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. (4) When the input data of all channels in the group are continuously zeros for 8192 LRCK cycles, DZF pin corresponding to the group goes to "H". DZF pin immediately goes to "L" if input data of any channel in the group is not zero after going DZF "H". Figure 20. Soft mute and zero detection
MS0097-E-01 - 34 -
2001/12
ASAHI KASEI
[AK4586]
Serial Control Interface
(1) 4-wire Serial Control Mode (I2C = "L") The internal registers may be either written or read by the 4-wire P interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, CAD1-0 are fixed to "00"), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN= "L" resets the registers to their default values. CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
WRITE
CDTI CDTO CDTI CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
READ
Hi-Z C1-0: R/W: A4-A0: D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Chip Address (Fixed to "00") READ/WRITE (0:READ, 1:WRITE) Register Address Control Data
Figure 21. 4-wire Serial Control I/F Timing
MS0097-E-01 - 35 -
2001/12
ASAHI KASEI
2
[AK4586]
(2) I C-bus Control Mode (I2C= "H") AK4586 supports the standard-mode I2C-bus (max:100kHz). Then AK4586 cannot be incorporated in a fast-mode I2C-bus system (max:400kHz). (2)-1. WRITE Operations Figure 22 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 28). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W). The most significant five bits of the slave address are fixed as "00100". The next two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0 pin) set them (Figure 23). If the slave address match that of the AK4586, the AK4586 generates the acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 29). A "1" for R/W bit indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the address for control registers of the AK4586. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 24). Those data after the second byte contain control data. The format is MSB first, 8bits (Figure 25). The AK4586 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 28). The AK4586 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4586 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 30) except for the START and the STOP condition.
S T A R T S T O P Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W= "0"
SDA
S
Slave Address A C K
Sub Address(n)
Figure 22. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins) Figure 23. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 24. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 25. Byte structure after the second byte
MS0097-E-01 - 36 -
2001/12
ASAHI KASEI
[AK4586]
(2)-2. READ Operations Set R/W bit = "1" for the READ operation of the AK4586. After transmission of a data, the master can read next address's data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4586 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. (2)-2-1. CURRENT ADDRESS READ The AK4586 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4586 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4586 discontinues transmission
S T A R T R/W= "1" S T O P Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Data(n)
Figure 26. CURRENT ADDRESS READ (2)-3-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues the start condition, slave address(R/W="0") and then the register address to read. After the register address's acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". Then the AK4586 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4586 discontinues transmission.
S T A R T R/W= "0" S T A R T S A C K Slave Address A C K R/W= "1" S T O P Data(n+1) A C K A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Sub Address(n)
Data(n)
Figure 27. RANDOM ADDRESS READ
MS0097-E-01 - 37 -
2001/12
ASAHI KASEI
[AK4586]
SDA
SCL S start condition P stop condition
Figure 28. START and STOP conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 29. Acknowledge on the I2C-bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 30. Bit transfer on the I2C-bus
MS0097-E-01 - 38 -
2001/12
ASAHI KASEI
[AK4586]
Mapping of Program Registers
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H Register Name Power Down & Reset Path Control Clock Mode Control Output Control Receiver Control I/F Format & ATT Speed LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control INT0 Mask INT1 Mask Receiver Status 0 Receiver Status 1 Channel Status Byte 0 Channel Status Byte 1 Channel Status Byte 2 Channel Status Byte 3 Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 D7 0 0 0 0 XFS96 0 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 MRFS0 MRFS1 RFS96 0 C7 C15 C23 C31 PC7 PC15 PD7 PD15 D6 0 0 CLKDIV SMUTE AFS96 0 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 MV0 MV1 V 0 C6 C14 C22 C30 DTSCD PC14 PD6 PD14 D5 0 LOOP1 OCKS1 TXE CS12 ATS1 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 MSTC0 MSTC1 STC 0 C5 C13 C21 C29 PC5 PC13 PD5 PD13 D4 0 LOOP0 OCKS0 BCU EFH1 ATS0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 MAUD0 MAUD1 AUDION 0 C4 C12 C20 C28 PC4 PC12 PD4 PD12 D3 PWVRN IPS1 ICKS1 OVFE EFH0 TDM ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 MDTS0 MDTS1 DTSCD 0 C3 C11 C19 C27 PC3 PC11 PD3 PD11 D2 PWADN IPS0 ICKS0 DZFM2 DEAU DIF2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 MAUT0 MAUT1 AUTO PEM C2 C10 C18 C26 PC2 PC10 PD2 PD10 D1 PWDAN OPS1 CM1 DZFM1 DEM1 DIF1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 MPAR0 MPAR1 PAR FS1 C1 C9 C17 C25 PC1 PC9 PD1 PD9 D0 RSTN OPS0 CM0 DZFM0 DEM0 DIF0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 MUNL0 MUNL1 UNLOCK FS0 C0 C8 C16 C24 PC0 PC8 PD0 PD8
Note: For addresses from 18H to 1FH, data is not written. When PDN goes to "L", the registers are initialized to their default values. When RSTN bit goes to "0", the internal timing is reset and DZF1-2 pins go to "H", but registers are not initialized to their default values. All data can be written to the register even if PWVRN, PWADN or PWDAN bit is "0".
MS0097-E-01 - 39 -
2001/12
ASAHI KASEI
[AK4586]
Register Definitions
Addr 00H Register Name Power Down & Reset R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 D3 PWVRN R/W 1 D2 PWADN R/W 1 D1 PWDAN R/W 1 D0 RSTN R/W 1
RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to "H", but registers are not initialized. 1: Normal operation PWDAN: Power-down control of DAC1-3 0: Power-down 1: Normal operation PWADN: Power-down control of ADC 0: Power-down 1: Normal operation PWVRN: Power-down control of reference voltage 0: Power-down. ADC, DAC and PLL are powered-down. 1: Normal operation
Addr 01H
Register Name Path Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 LOOP1 R/W 0
D4 LOOP0 R/W 0
D3 IPS1 R/W 0
D2 IPS0 R/W 0
D1 OPS1 R/W 0
D0 OPS0 R/W 0
OPS1-0: Output Through Data Select (Table 12) Default: "00", RX1 IPS1-0: Input Recovery Data Select (Table 11) Default: "00", RX1 LOOP1-0: Loopback mode enable 00: Normal (No loop back) 01: LIN LOUT1, LOUT2, LOUT3, LOUT4 RIN ROUT1, ROUT2, ROUT3, ROUT4 The ADC digital output (RX data in the PLL mode) is connected to the digital DAC input. In this mode, the input DAC data to SDTI1-3 is ignored. 10: SDTI1(L) SDTI2(L), SDTI3(L) SDTI1(R) SDTI2(R), SDTI3(R) In this mode the input DAC data to SDTI2-3 is ignored. 11: N/A LOOP1-0 should be set to "00" at TDM bit "1".
MS0097-E-01 - 40 -
2001/12
ASAHI KASEI
[AK4586]
Addr 02H
Register Name Clock Mode Control R/W Default
D7 0 RD 0
D6 CLKDIV R/W 0
D5 OCKS1 R/W 0
D4 OCKS0 R/W 0
D3 ICKS1 R/W 0
D2 ICKS0 R/W 0
D1 CM1 R/W 0
D0 CM0 R/W 0
CM1-0: Master Clock Operation Mode Select (Table 1) Default: "00", mode 0 OCKS1-0: Master Clock Output Frequency Select at PLL mode (Table 2) Default: "00", mode 0 ICKS1-0: Master Clock Input Frequency Select at X'tal mode (Table 4) Default: "00", mode 0 CLKDIV: Master Clock Output Select at X'tal mode (Table 5) 0: Same frequency as crystal oscillator 1: Half frequency of crystal oscillator
MS0097-E-01 - 41 -
2001/12
ASAHI KASEI
[AK4586]
Addr 03H
Register Name Output Control R/W Default
D7 0 RD 0
D6 SMUTE R/W 0
D5 TXE R/W 1
D4 BCU R/W 0
D3 OVFE R/W 0
D2 DZFM2 R/W 1
D1 DZFM1 R/W 1
D0 DZFM0 R/W 1
DZFM2-0: Zero detect mode select (Table 16) Initial: "111", disable OVFE: Overflow detection enable 0: Disable, pin#20 becomes DZF2 pin. 1: Enable, pin#20 becomes OVF pin. BCU: Block Start and C/U/V Output Mode When BCU=1, the 4 output pins change another function. DZF1 Pin Block start signal DZF2 Pin C bit INT1 Pin U bit TX Pin V bit The block signal goes high at the start of frame 0 and remains high until the end of frame 31. (B, C, U, V output timing at RX mode, master mode)
B
C (or U,V)
C(R191)
C(L0) 1/4fs
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
LRCK SDTO (I2S) SDTO (except I2S)
L191
R191
L0
R0
R30
L31
R31
R190
L191
R191
L0
L30
R30
L31
TXE: TX Output Enable 0: Disable. TX output is "L". 1: Enable SMUTE: Soft Mute Enable (Figure 20) 0: Normal operation 1: All DAC outputs soft-muted
MS0097-E-01 - 42 -
2001/12
ASAHI KASEI
[AK4586]
Addr 04H
Register Name Receiver Control R/W Default
D7 XFS96 R/W 0
D6 AFS96 R/W 1
D5 CS12 R/W 0
D4 EFH1 R/W 0
D3 EFH0 R/W 1
D2 DEAU R/W 1
D1 DEM1 R/W 0
D0 DEM0 R/W 1
DEM1-0: De-emphasis Control (Table 9) The setting of DEM1-0 bits is ignored at DEAU bit "1". Default: "01", OFF DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable EFH1-0: Interrupt 0 Pin Hold Count Select 00: 512 LRCK 01: 1024 LRCK (default) 10: 2048 LRCK 11: 4096 LRCK CS12: Channel Status Select 0: Channel 1 1: Channel 2 Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS1 and FS0. AFS96: Sampling Speed Mode Auto Setting Mode Enable (Table 3) 0: Disable, sampling mode is set by XFS96 bit. 1: Enable, sampling mode is automatically set by the register value of RFS96 bit at PLL mode. XFS96: ADC and DAC Sampling Speed Mode Select (X'tal Mode or AFS96= "0", Table 3) 0: Normal speed mode 1: Double speed mode The sampling speed mode is defined by RFS96 and the setting of XFS96 is ignored at AFS96 bit "1" in the PLL mode.
Addr 05H
Register Name I/F Format & ATT Speed R/W Default
D7 0 RD 0
D6 0 RD 0
D5 ATS1 R/W 0
D4 ATS0 R/W 0
D3 TDM R/W 0
D2 DIF2 R/W 1
D1 DIF1 R/W 0
D0 DIF0 R/W 0
DIF2-0: Audio Data Format Control (Table 14, Table 15) Default: "100", mode 4 TDM: TDM Format Select 0: Normal format 1: TDM format ATS1-0: Digital attenuator transition time setting (Table 18) Default: "00", mode 0
MS0097-E-01 - 43 -
2001/12
ASAHI KASEI
[AK4586]
Addr 06H 07H 08H 09H 0AH 0BH
Register Name LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control R/W Default
D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 R/W 0
D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 R/W 0
D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 R/W 0
D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 R/W 0
D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 R/W 0
D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 R/W 0
D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 R/W 0
D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 R/W 0
ATT7-0: Attenuation Level (Table 17) Default: all "0" (0dB)
MS0097-E-01 - 44 -
2001/12
ASAHI KASEI
[AK4586]
Addr Register Name 0CH INT0 Mask R/W Default
D7 MRFS0 R/W 1
D6 MV0 R/W 1
D5 MSTC0 R/W 1
D4 MAUD0 R/W 1
D3 MDTS0 R/W 1
D2 MAUT0 R/W 1
D1 MPAR0 R/W 0
D0 MUNL0 R/W 0
MULK0: Mask Enable for UNLOCK bit (Default: 0) 0: Mask disable 1: Mask enable MPAR0: Mask Enable for PAR bit (Default: 0) 0: Mask disable 1: Mask enable MAUT0: Mask Enable for AUTO bit (Default: 1) 0: Mask disable 1: Mask enable MDTS0: Mask Enable for DTSCD bit (Default: 1) 0: Mask disable 1: Mask enable MAUD0: Mask Enable for AUDIO bit (Default: 1) 0: Mask disable 1: Mask enable MSTC0: Mask Enable for STC bit (Default: 1) 0: Mask disable 1: Mask enable MV0: Mask Enable for V bit (Default: 1) 0: Mask disable 1: Mask enable MRFS0: Mask Enable for RFS96 bit (Default: 1) 0: Mask disable 1: Mask enable
Addr Register Name 0DH INT1 Mask R/W Default
D7 MRFS1 R/W 1
D6 MV1 R/W 0
D5 MSTC1 R/W 1
D4 MAUD1 R/W 0
D3 MDTS1 R/W 0
D2 MAUT1 R/W 0
D1 MPAR1 R/W 1
D0 MUNL1 R/W 1
MULK1: Mask Enable for UNLOCK bit (Default: 1) 0: Mask disable 1: Mask enable MPAR1: Mask Enable for PAR bit (Default: 1) 0: Mask disable 1: Mask enable MAUT1: Mask Enable for AUTO bit (Default: 0) 0: Mask disable 1: Mask enable MDTS1: Mask Enable for DTSCD bit (Default: 0) 0: Mask disable 1: Mask enable MAUD1: Mask Enable for AUDIO bit (Default: 0) 0: Mask disable 1: Mask enable MSTC1: Mask Enable for STC bit (Default: 1) 0: Mask disable 1: Mask enable MV1: Mask Enable for V bit (Default: 0) 0: Mask disable 1: Mask enable MRFS1: Mask Enable for RFS96 bit (Default: 1) 0: Mask disable 1: Mask enable
MS0097-E-01 - 45 -
2001/12
ASAHI KASEI
[AK4586]
Addr 0EH
Register Name Receiver status 1 R/W Default
D7 RFS96 RD 0
D6 V RD 0
D5 STC RD 0
D4 AUDION RD 0
D3 DTSCD RD 0
D2 AUTO RD 0
D1 PAR RD 0
D0 UNLOCK RD 0
UNLOCK: PLL Lock Status 0: Lock
1: Unlock
PAR: Parity Error or Biphase Error Status 0: No error 1: Error It is "1" if parity error or biphase error is detected in the sub-frame. AUTO: Non-PCM Bit Steam Auto Detect 0: No detect 1: Detect DTSCD: DTS-CD Bit Steam Auto Detect 0: No detect 1: Detect AUDION: Audio Bit Output 0: Audio 1: Non audio This bit is made by encoding channel status bits. STC: Sampling Frequency or Pre-emphasis Information Change Detect 0: No detect 1: Detect It is "1" if FS1, FS0 or PEM bit changes. V: Validity Bit 0: Valid
1: Invalid
RFS96: 96kHz Sampling Detect at Recovery Mode 0: fs=48kHz or less 1: fs=88.2kHz or more
Addr 0FH
Register Name Receiver status 2 R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3 0 RD 0
D2 PEM RD 0
D1 FS1 RD 0
D0 FS0 RD 0
FS1-0: Sampling Frequency Bit Output This bit is made by encoding channel status bits. PEM: Pre-emphasis Bit Output 0: OFF 1: ON This bit is made by encoding channel status bits.
MS0097-E-01 - 46 -
2001/12
ASAHI KASEI
[AK4586]
Addr 10H 11H 12H 13H
Register Name Channel Status Byte 0 Channel Status Byte 1 Channel Status Byte 2 Channel Status Byte 3 R/W Default
D7 C7 C15 C23 C31
D6 C6 C14 C22 C30
D5 C5 C13 C21 C29
D4 C4 C12 C20 C28
D3 C3 C11 C19 C27
D2 C2 C10 C18 C26
D1 C1 C9 C17 C25
D0 C0 C8 C16 C24
RD Not initialized
C31-0: Channel Status Byte 3-0
Addr 14H 15H 16H 17H
Register Name Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 R/W Default
D7 PC7 PC15 PD7 PD15
D6 PC6 PC14 PD6 PD14
D5 PC5 PC13 PD5 PD13
D4 PC4 PC12 PD4 PD12
D3 PC3 PC11 PD3 PD11 RD Not initialized
D2 PC2 PC10 PD2 PD10
D1 PC1 PC9 PD1 PD9
D0 PC0 PC8 PD0 PD8
PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1
MS0097-E-01 - 47 -
2001/12
ASAHI KASEI
[AK4586]
Burst Preambles in Non-PCM Bitstreams
sub-frame of IEC60958
0 preamble 34 Aux. 78 11 12 LSB 27 28 29 30 31 MSB V U C P
16 bits of bitstream
0 15
Pa Pb Pc Pd
Burst_payload
stuffing
repetition time of the burst
Figure 31. Data structure in IEC60958 Preamble word Pa Pb Pc Pd Length of field 16 bits 16 bits 16 bits 16 bits Contents Value sync word 1 0xF872 sync word 2 0x4E1F Burst info see Table 20 Length code numbers of bits Table 19. Burst preamble words
MS0097-E-01 - 48 -
2001/12
ASAHI KASEI
[AK4586]
Bits of Pc Value 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-26 27 28 29-31 0 0 1
Contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension reserved MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved (reserved for MPEG-4 AAC data) MPEG-2 AAC data reserved reserved, shall be set to "0" error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors data type dependent info bit stream number, shall be set to "0" Table 20. Fields of burst info Pc
Repetition time of burst in IEC60958 frames 4096 1536
384 1152 1152 384 1152 512 1024 2048 512 1024 512 1024
5, 6 7
8-12 13-15
0
MS0097-E-01 - 49 -
2001/12
ASAHI KASEI
[AK4586]
Non-PCM Bitstream timing
1) When Non-PCM preamble is not coming within 4096 frames,
PDN pin
Bit stream
Pa Pb Pc1 Pd1 Repetition time
Pa Pb Pc2 Pd2 >4096 frames
Pa Pb Pc3 Pd3
AUTO bit
Pc Register
"0"
Pc1
Pc2
Pc3
Pd Register
"0"
Pd1
Pd2
Pd3
Figure 32. Timing example 1
2) When Non-PCM bitstream stops (when MULK0=0),
INT0 pin <20mS (Lock time) Bit stream Pa Pb Pc1 Pd1 Stop 2~3 Syncs (B,M or W) AUTO bit Pc Register
Pc0
Pc1
Pcn
Pd Register
Pd0
Pd1
Pdn
Figure 33. Timing example 2
MS0097-E-01 - 50 -
2001/12
ASAHI KASEI
[AK4586]
SYSTEM DESIGN
Figure 34 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: TVDD=3.3V, Master mode, 4-wire serial control mode, DZFM2-0 = "100"
5
(S/PDIF sources)
+ (Shield) (Shield) (Shield) 10u 0.1u
Power-down Control
RX1 43 PDN 44
I2C 42
TST 40
RX3 39
RX4 37
PVSS 36
R 35
C C 10u
X'tal 1 0.1u + 2 3 4 XTO XTI
SLAVE 38
PVDD 34 RIN 33 LIN 32 ROUT1 31 LOUT1 30 ROUT2 29 MUTE MUTE MUTE MUTE MUTE MUTE 0.1u 2.2u + LOUT2 28 ROUT3 27 LOUT3 26 DZF1 25 VCOM 24 VREFH 23 + 0.1u 10u 22 AVDD
DVDD DVSS TVDD TX MCKO LRCK BICK
Digital 3.3V (S/PDIF out)
+ 10u 0.1u
5 6 7 8
RX2 41
AK4586
12 SDTI2
13 SDTI3
16 CDTO
18 CCLK
P
Analog 5V Digital Ground Analog Ground
Figure 34. Typical Connection Diagram Notes: - "C" depends on the crystal. - AVSS, DVSS and PVSS must be connected the same analog ground plane. - Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance. - In case of coaxial input, ground of RCA connector and terminator should be connected to PVSS of the AK4586 with low impedance on PC board.
MS0097-E-01 - 51 -
21 AVSS 5
Audio DSP (MPEG/ AC3)
9
10 SDTO 11 SDTI1 17 CDTI 14 INT0 19 CSN 20 DZF2 15 INT1
18k
2001/12
ASAHI KASEI
[AK4586]
1. Grounding and Power Supply Decoupling The AK4586 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and PVDD are usually supplied from analog supply in system. Alternatively if AVDD, DVDD and PVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and PVSS of the AK4586 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4586 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1F ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2F parallel with a 0.1F ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4586. 3. Analog Inputs ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp (typ). The ADC output data format 2's compliment. The DC offset is removed by the internal HPF. The AK4586 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4586 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
MS0097-E-01 - 52 -
2001/12
ASAHI KASEI
[AK4586]
PACKAGE
44pin LQFP (Unit: mm)
12.800.30 1.70max 00.2 10.00 33 34 23 22 12.800.30 10.00 44 1 0.370.10 010 11 0.170.05 12 0.600.20 0.15
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
Package & Lead frame material
MS0097-E-01 - 53 -
0.80
2001/12
ASAHI KASEI
[AK4586]
MARKING
AK4586VQ XXXXXXX
1
1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4586VQ 4) Asahi Kasei Logo IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0097-E-01 - 54 -
2001/12

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